From 137a9ce8c7e9166495bd8835c42fdd7dc291649b Mon Sep 17 00:00:00 2001 From: "kaf24@firebug.cl.cam.ac.uk" Date: Sat, 30 Sep 2006 11:11:54 +0100 Subject: [PATCH] [HVM] Add RDMSR/WRMSR instruction emulation to VMXAssist decoder AP of PAE SMP windows will use it to set NX bit in EFER. Signed-off-by: Xin Li --- tools/firmware/vmxassist/vm86.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/tools/firmware/vmxassist/vm86.c b/tools/firmware/vmxassist/vm86.c index d6cfb500e8..8c620a4d5c 100644 --- a/tools/firmware/vmxassist/vm86.c +++ b/tools/firmware/vmxassist/vm86.c @@ -1230,6 +1230,18 @@ pushrm(struct regs *regs, int prefix, unsigned modrm) enum { OPC_INVALID, OPC_EMULATED }; +#define rdmsr(msr,val1,val2) \ + __asm__ __volatile__( \ + "rdmsr" \ + : "=a" (val1), "=d" (val2) \ + : "c" (msr)) + +#define wrmsr(msr,val1,val2) \ + __asm__ __volatile__( \ + "wrmsr" \ + : /* no outputs */ \ + : "c" (msr), "a" (val1), "d" (val2)) + /* * Emulate a single instruction, including all its prefixes. We only implement * a small subset of the opcodes, and not all opcodes are implemented for each @@ -1288,6 +1300,12 @@ opcode(struct regs *regs) if (!movcr(regs, prefix, opc)) goto invalid; return OPC_EMULATED; + case 0x30: /* WRMSR */ + wrmsr(regs->ecx, regs->eax, regs->edx); + return OPC_EMULATED; + case 0x32: /* RDMSR */ + rdmsr(regs->ecx, regs->eax, regs->edx); + return OPC_EMULATED; default: goto invalid; } -- 2.30.2